With respect to prior bottom-up methods for fabricating nanowires, there has been much progress in research in synthesizing nanowires, and its electrical, optical and physical characteristics, but there are still limitations in applying the methods for aligning this in desired locations in integrated systems.
On the contrary, overcoming problems with respect to alignments are possible when fabricating nanowires in a top-down method, but they are fabricated through SOI substrates and e-beam lithography and thus have problems in productivity of nanowire devices.
Recently, various methods regarding fabricating nanowires using single crystal silicon substrates, not SOI substrates, are being introduced, but devices using these are realized on rigid substrates or even when realized on flexible substrates, they mostly have bottom-gate and top-gate structures.
But the nanowires, as its diameter becomes smaller, electrostatic control effects of nanowire devices become excellent, but have problems of parasitic resistance of source/drain becoming greater.
Also, as the size of devices become smaller, channel lengths of transistors formed at device forming regions, especially active regions becoming shorter, and thus influence of source/drain regions to electric fields of channel regions become significant, and problems of short channel effects, from which channel driving performance by gate electrodes deteriorates, occur.